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1A Ultra Low Dropout Linear Regulator with Programmable Current Limiting
ISL80121-5
The ISL80121-5 is a low dropout voltage, single output LDO with programmable current limiting. This LDO operates from input voltages of 2.2V to 6V. The ISL80121-5 has a nominal output voltage of 5V. Other custom voltage options are available upon request. A sub-micron BiCMOS process is utilized for this product family to deliver the best in class analog performance and overall value. The programmable current limiting improves system reliability of applications. An external capacitor on the soft-start pin provides an adjustable soft-starting ramp. The ENABLE feature allows the part to be placed into a low quiescent current shutdown mode. This CMOS LDO will consume significantly lower quiescent current as a function of load compared to bipolar LDOs, which translates into higher efficiency and packages with smaller footprints. Quiescent current is modestly compromised to achieve a very fast load transient response.
Features
* 1.8% VOUT Accuracy Guaranteed Over Line, Load and TJ = -40C to +125C * Very Low 130mV Dropout Voltage at VIN = 5.0V * High Accuracy Current Limit Programmable up to 1.75A * Very Fast Transient Response * 200VRMS Output Noise * Power Good Output * Programmable Soft-starting * Over-Temperature Protection * Small 10 Ld DFN Package
Applications
* USB devices * Telecommunications and Networking * Medical Equipment * Instrumentation Systems * Routers and Switchers * Gaming
Typical Applications
5.4V 10% VIN CIN 10F 8 ISL80121-5 10 9 VIN VIN VOUT VOUT 1 2 5.0V 1.8% VOUT COUT 10F 3 RPG 100k ON ENABLE SS GND 5 CSS PG 4 PGOOD OFF 7 6 ENABLE SS GND 5 PG 4 PGOOD 5.4V 10% VIN CIN 10F 8 RISET 10k ISL80121-5 10 9 VIN VIN ISET VOUT VOUT SENSE 1 2 3 RPG 100k RSENSE 10 COUT 10F 5.0V 1.8% VOUT
ISET
SENSE
ON OFF
7 6 CSS
I
LIMIT
= 0.75A
(default)
2.9 I LIMIT = 0.75 + -----------------------------------R SET ( k )
December 8, 2010 FN7713.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2010. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners
ISL80121-5 Block Diagram
SS THERMAL SHUTDOWN VIN
CURRENT LIMITER
VOUT
ISET PGOOD VOLTAGE REFERENCE POWER GOOD
ADJ ADJUSTABLE VOLTAGE VERSION ENABLE SENSE FIXED VOLTAGE VERSION
GND
Ordering Information
PART NUMBER (Notes 1, 2, 4) ISL80121IR50Z NOTES: 1. Add "-T*" suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. The 1.5V, 3.3V and 5V fixed output voltages will be released in the future. Please contact Intersil Marketing for more details. 4. For Moisture Sensitivity Level (MSL), please see device information page for ISL80121-5. For more information on MSL, please see Technical Brief TB363. DZAD PART MARKING VOUT VOLTAGE (Note 3) 5.0V TEMP. RANGE (C) -40 to +125 PACKAGE (Pb-Free) 10 Ld 3x3 DFN PKG DWG. # L10.3x3
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FN7713.1 December 8, 2010
ISL80121-5 Pin Configuration
ISL80121-5 (10 LD 3x3 DFN) TOP VIEW
VOUT VOUT SENSE PG GND 1 2 3 4 5 PAD 10 VIN 9 8 7 6 VIN ISET ENABLE SS
Pin Descriptions
PIN NUMBER 1, 2 3 PIN NAME VOUT SENSE DESCRIPTION Output voltage. A minimum 10F X5R/X7R output capacitor is required for stability. See "External Capacitor Requirements" on page 8 in the "Functional Description" for more details. Remote voltage sense for internally fixed VOUT options. Parasitic resistance between the VOUT pin and the load causes small voltage drops which degrade VOUT accuracy. For applications that require a stiff VOUT, connect the sense pin to the load. VOUT in regulation signal. Logic low indicates VOUT is not in regulation, and must be grounded if not used. Ground. External capacitor adjusts in-rush current. VIN-independent chip enable. TTL and CMOS compatible. Current limit setting. Current limit is 0.75mA when this pin is left floating. This default value can be increased by tying RSET to GND, or decreased by tying RSET to VIN. See "Programmable Current Limit" on page 7 in the "Functional Description" for more details. Do not short this pin to ground. Input supply. A minimum of 10F X5R/X7R input capacitor is required for stability. See "External Capacitor Requirements" on page 8 in "Functional Description" for more details. EPAD at ground potential. Soldering it directly to GND plane is optional.
4 5 6 7 8
PG GND SS ENABLE ISET
9, 10 -
VIN EPAD
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FN7713.1 December 8, 2010
ISL80121-5
Absolute Maximum Ratings
(Note 7)
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) 10 Ld 3x3 DFN Package (Notes 5, 6). . . . . 51 7 Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
VIN Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V VOUT Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V PG, ENABLE, SENSE, SS, ISET Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V ESD Rating Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . .2.5kV Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . 250V Latch Up (Tested per JESD78). . . . . . . . . . . . . . . . . . . . . . .100mA @ 85C
Recommended Operating Conditions (Note 8)
Junction Temperature Range (TJ) . . . . . . . . . . . . . . . . . . .-40C to +125C VIN Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.2V to 6V VOUT Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800mV to 5V PG, ENABLE, SENSE, SS, ISET Relative to GND. . . . . . . . . . . . . . . . 0V to 6V PG Sink Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 5. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 6. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 7. Absolute maximum voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6V of 1%. 8. Electromigration specification defined as lifetime average junction temperature of +110C where max rated DC current = lifetime average current.
Electrical Specifications Unless otherwise noted, all parameters are established over the following specified conditions: VIN = VOUT + 0.4V, VOUT = 5.0V, CIN = COUT = 10F, TJ = +25C, ILOAD = 0A. Applications must follow thermal guidelines of the package to determine worst case junction temperature. Please refer to "Functional Description" on page 7 and Tech Brief TB379. Boldface limits apply over the operating temperature range, -40C to +125C. Pulse load techniques used by ATE to ensure TJ = TA defines established limits.
PARAMETER SYMBOL TEST CONDITIONS MIN (Note 9) TYP MAX (Note 9) UNITS
DC CHARACTERISTICS
DC Output Voltage Accuracy DC Input Line Regulation DC Output Load Regulation Ground Pin Current VOUT VOUT/VIN VOUT IQ VOUT + 0.4V < VIN < 6V; 0A < ILOAD < 1A VOUT + 0.4V < VIN < 6.0V, VOUT = 5.0V 0A < ILOAD < 1A ILOAD = 0A, 2.2V < VIN < 6V ILOAD = 1A, 2.2V < VIN < 6V Ground Pin Current in Shutdown Dropout Voltage (Note 10) Output Current Limit ISHDN VDO ILIMIT ENABLE Pin = 0.2V, VIN = 6V ILOAD = 1A, VIN = 5.0V, VSENSE = 0V VOUT = 4.75V, VOUT + 0.4V < VIN < 6V, ISET is floating VOUT = 4.75V, VOUT + 0.4V < VIN < 6V, RSET = 19.33k Thermal Shutdown Temperature Thermal Shutdown Hysteresis (Rising Threshold) TSD TSDn VOUT + 0.4V < VIN < 6V VOUT + 0.4V < VIN < 6V 0.66 -1 3 5 0.2 90 0.75 0.9 160 30 5 7 12 130 0.84 -1.8 -1.8 1 % % % mA mA A mV A A
C C
AC CHARACTERISTICS
Input Supply Ripple Rejection PSRR f = 1kHz, ILOAD = 1A f = 120Hz, ILOAD = 1A Output Noise Voltage ILOAD = 10mA, BW = 10Hz < f < 100kHz 58 62 210 dB dB VRMS
ENABLE PIN CHARACTERISTICS
Turn-on Threshold Hysteresis (Rising Threshold) VEN(HIGH) VEN(HYS) 2.2V < VIN < 6V 2.2V < VIN < 6V 0.3 10 0.8 80 1.0 200 V mV
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FN7713.1 December 8, 2010
ISL80121-5
Electrical Specifications Unless otherwise noted, all parameters are established over the following specified conditions: VIN = VOUT + 0.4V, VOUT = 5.0V, CIN = COUT = 10F, TJ = +25C, ILOAD = 0A. Applications must follow thermal guidelines of the package to determine worst case junction temperature. Please refer to "Functional Description" on page 7 and Tech Brief TB379. Boldface limits apply over the operating temperature range, -40C to +125C. Pulse load techniques used by ATE to ensure TJ = TA defines established limits. (Continued)
PARAMETER Enable Pin Turn-on Delay Enable Pin Leakage Current SYMBOL tEN TEST CONDITIONS COUT = 10F, ILOAD = 1A VIN = 6V, EN = 3V MIN (Note 9) TYP 100 1 MAX (Note 9) UNITS s A
SOFT-START CHARACTERISTICS
Reset Pull-Down Current Soft-Start Charge Current IPD ICHG EN = 0V, SS = 1V 0.5 -3.3 1 -2 1.3 -0.8 mA A
PG PIN CHARACTERISTICS
VOUT PG Flag Threshold VOUT PG Flag Hysteresis PG Flag Low Voltage PG Flag Leakage Current NOTES: 9. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 10. Dropout is defined by the difference in supply VIN and VOUT when the output is below its nominal regulation. 11. Minimum capacitor of 10F X5R/X7R on VIN and VOUT required for stability. 12. If the current limit for in-rush current is acceptable in application, do not use this feature. Used only when large bulk capacitance required on VOUT for application. ISINK = 500A VIN = 6V, PG = 6V 75 85 4 47 0.05 100 1 92 %VOUT % mV A
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FN7713.1 December 8, 2010
ISL80121-5 Typical Operating Performance
150
Unless otherwise noted: VIN = 5.4V, VOUT = 5.0V, CIN = COUT = 10F, TJ = +25C, IL = 0A.
1.8 1.2
120 DROPOUT (mV) +125C +25C DVOUT (%) 90 0.6 0 -0.6 -40C 30 -1.2 -1.8 -50
60
0
0
0.2
0.4 0.6 LOAD CURRENT (A)
0.8
1.0
-25
0
25
50
75
100
125
150
JUNCTION TEMPERATURE (C)
FIGURE 1. DROPOUT VOLTAGE vs LOAD
FIGURE 2. OUTPUT VOLTAGE vs TEMPERATURE
1.8 1.2 0.6 DVOUT (%) 0 -0.6 -1.2 -1.8 +125C -40C +25C GROUND CURRENT (mA)
3.30 3.25 3.20 3.15 3.10 3.05 3.00 2.95 2.90 0 0.25 0.50 OUTPUT CURRENT (mA) 0.75 1.00 2.85 0 0.2 0.4 0.6
+25C +125C
-40C
0.8
1
LOAD CURRENT (A)
FIGURE 3. OUTPUT VOLTAGE vs OUTPUT CURRENT
FIGURE 4. GROUND CURRENT vs LOAD CURRENT
5.0 4.5 4.0 GROUND CURRENT (A) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -40 PG (5V/DIV) -25 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125 TIME (2ms/DIV) VOUT (5V/DIV) VIN = 6V EN (2V/DIV)
SS (2V/DIV)
FIGURE 5. SHUTDOWN CURRENT vs TEMPERATURE
FIGURE 6. ENABLE START-UP
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FN7713.1 December 8, 2010
ISL80121-5 Typical Operating Performance
1.0 0.9 0.8 CURRENT LIMIT (A) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -40 10 60 TEMPERATURE (C) 110 TIME (50s/DIV) IOUT = 10mA IOUT = 500mA VOUT (50V/DIV) RSET = OPEN RSET = 20k
Unless otherwise noted: VIN = 5.4V, VOUT = 5.0V, CIN = COUT = 10F, TJ = +25C, IL = 0A. (Continued)
FIGURE 7. CURRENT LIMIT vs TEMPERATURE
FIGURE 8. LOAD TRANSIENT RESPONSE
60 100mA LOAD 1A LOAD MAGNITUDE (dB) 30 MAGNITUDE (dB) 40 30 20 50
LOAD = 100mA COUT = 100F COUT = 47F
40
20
10
COUT = 22F 10 0 10 COUT = 10F 100 1k 10k FREQUENCY (Hz) 100k 1M
0 10
100
1k 10k FREQUENCY (Hz)
100k
1M
FIGURE 9. PSRR vs LOAD
FIGURE 10. PSRR vs C OUT
Functional Description
Input Voltage Requirements
The ISL80121-5 is optimized for 5V output, and can operate from input voltages of 2.2V to 6V. Due to the nature of an LDO, VIN must be some margin higher than VOUT plus dropout at the maximum rated current of the application if active filtering (PSRR) is expected from VIN to VOUT. The generous dropout specification of this family of LDOs allows applications to design for a level of efficiency that can accommodate profiles smaller than the TO220/263.
The current limit is set at 0.75A by default when the ISET pin is left floating. This limit can be increased by tying a resistor RSET from the ISET pin to ground. The current limit is determined by RSET as shown in Equation 1:
2.9 I LIMIT = 0.75 + -------------------------R SET ( k ) (EQ. 1)
Programmable Current Limit
The ISL80121-5 protects against overcurrent due to short-circuit and overload conditions applied to the output. When this happens, the LDO performs as a constant current source. If the short-circuit or overload condition is removed, the output returns to normal voltage regulation operation.
Figure 11 shows the relationship between RSET and the current limit when the RSET is tied from ISET pin to GND. Do not short this pin to ground. Increasing the current limit past 1.75A may cause damage to the part and is highly discouraged.
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FN7713.1 December 8, 2010
ISL80121-5
1.7 1.5 1.3 1.1 0.9 0.7
CURRENT LIMIT (A)
source greater than VIN. PGOOD goes low when the output voltage drops below 84% of the nominal output voltage, the current limit faults, or the input voltage is too low. PGOOD functions during shutdown, but not during thermal shutdown. For applications not using this feature, connect this pin to ground.
Soft-Start Operation
The soft-start circuit controls the rate at which the output voltage rises up to regulation at power-up or LDO enable. This start-up ramp time can be set by adding an external capacitor from the SS pin to ground. An internal 2A current source charges up this CSS and the feedback reference voltage is clamped to the voltage across it. The start-up time is set by Equation 3:
( C SS x0.5 ) T start = -------------------------2A (EQ. 3)
2
20 RSET (k)
200
FIGURE 11. INCREASING ILIMIT (R SET TO GND)
The current limit can be decreased from the 0.75A default by tying RSET from the ISET pin to VIN. The current limit is then determined by both RSET and VIN following Equation 2:
2.9 x ( 2 x V IN - 1 ) I LIMIT = 0.75 - ---------------------------------------------R SET ( k ) (EQ. 2)
Equation 4 determines the CSS required for a specific start-up in-rush current, where VOUT is the output voltage, COUT is the total capacitance on the output and IINRUSH is the desired in-rush current.
( V OUT xC OUT x2A ) ) C SS = ---------------------------------------------------I INRUSH x0.5V (EQ. 4)
Figure 12 shows the relationship between RSET and the current limit when RSET is tied from the ISET pin to VIN for VIN = 5.4V.
0.75 0.65 0.55 CURRENT LIMIT (A) 0.45 0.35 0.25 0.15 0.05 -0.05 40 400
The external capacitor is always discharged to ground at the beginning of start-up or enabling.
External Capacitor Requirements
External capacitors are required for proper operation. Careful attention must be paid to the layout guidelines and selection of capacitor type and value to ensure optimal performance.
OUTPUT CAPACITOR
The ISL80121-5 applies state-of-the-art internal compensation to keep the selection of the output capacitor simple for the customer. Stable operation over full temperature, VIN range, VOUT range and load extremes are guaranteed for all capacitor types and values assuming a minimum of 10F X5R/X7R is used for local bypass on VOUT. This output capacitor must be connected to the VOUT and GND pins of the LDO with PCB traces no longer than 0.5cm. There is a growing trend to use very-low ESR multilayer ceramic capacitors (MLCC) because they can support fast load transients and also bypass very high frequency noise from other sources. However, the effective capacitance of MLCCs drops with applied voltage, age, and temperature. X7R and X5R dieletric ceramic capacitors are strongly recommended as they typically maintain a capacitance range within 20% of nominal voltage over full operating ratings of temperature and voltage. Additional capacitors of any value in ceramic, POSCAP, alum/tantalum electrolytic types may be placed in parallel to improve PSRR at higher frequencies and/or load transient AC output voltage tolerances.
RSET (k)
FIGURE 12. DECREASING ISET (R SET TO VIN)
Enable Operation
The Enable turn-on threshold is typically 800mV with 80mV of hysteresis. An internal pull-up or pull-down resistor to change these values is available upon request. As a result, this pin must not be left floating, and should be tied to VIN if not used. A 1k to 10k pull-up resistor is required for applications that use open collector or open drain outputs to control the Enable pin. The Enable pin may be connected directly to VIN for applications with outputs that are always on.
Power-Good Operation
PGOOD is a logic output that indicates the status of VOUT, current limit tripping, and VIN. The PGOOD flag is an open-drain NMOS that can sink up to 10mA during a fault condition. The PGOOD pin requires an external pull-up resistor typically connected to the VOUT pin. The PGOOD pin should not be pulled up to a voltage
INPUT CAPACITOR
For proper operation, a minimum capacitance of 10F X5R/X7R is required at the input. This ceramic input capacitor must be connected to the VIN and GND pins of the LDO with PCB traces no longer than 0.5cm.
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FN7713.1 December 8, 2010
ISL80121-5
Power Dissipation and Thermals
The junction temperature must not exceed the range specified in the "Recommended Operating Conditions" on page 4. The power dissipation can be calculated by using Equation 5:
P D = ( V IN - V OUT ) x I OUT + V IN x I GND (EQ. 5)
The DFN package uses the copper area on the PCB as a heat-sink. The EPAD of this package must be soldered to the copper plane (GND plane). Figure 13 shows a curve for the JA of the DFN package for different copper area sizes.
46 44 JA (C/W)
The maximum allowable junction temperature, TJ(MAX) and the maximum expected ambient temperature, TA(MAX) determine the maximum allowable power dissipation, as shown in Equation 6:
P D ( MAX ) = ( T J ( MAX ) - T A ) JA (EQ. 6)
42 40 38 36 34 2
JA is the junction-to-ambient thermal resistance. For safe operation, enure that the power dissipation PD, calculated from Equation 5, is less than the maximum allowable power dissipation PD(MAX).
4
6
8
10
12
14
16
18
20
22
24
EPAD-MOUNT COPPER LAND AREA ON PCB, mm2
FIGURE 13. 3mmx3mm 10 LD DFN ON 4-LAYER PCB WITH THERMAL VIAS JA vs EPAD-MOUNT COPPER LAND AREA ON PCB
Thermal Fault Protection
The power level and the thermal impedance of the package (+48C/W for DFN) determine when the junction temperature exceeds the thermal shutdown temperature. In the event that the die temperature exceeds around +160C, the output of the LDO will shut down until the die temperature cools down to about +130C.
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FN7713.1 December 8, 2010
ISL80121-5 Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision.
DATE 12/6/10 REVISION FN7713.1 CHANGE 1. In "Block Diagram" on page 2: a. Added "ADJ adjustable voltage version" Pin. Added "fixed voltage version" to "SENSE" pin 2. On page 4: "Ground Pin Current" Test Conditions a. Replaced "VOUT+0.4V" with "2.2V" on both lines Initial Release.
12/2/10
FN7713.0
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL80121-5 To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff FITs are available from our website at: http://rel.intersil.com/reports/sear
For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com
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FN7713.1 December 8, 2010
ISL80121-5
Package Outline Drawing
L10.3x3
10 LEAD DUAL FLAT PACKAGE (DFN) Rev 6, 09/09
3.00 A B 1 6 PIN 1 INDEX AREA 2 2.00 8x 0.50 3.00 6 PIN #1 INDEX AREA
10 x 0.23
4
(4X)
0.10
1.60
TOP VIEW
BOTTOM VIEW (4X)
10x 0.35 4 0.10 M C A B
0.415 0.23
PACKAGE OUTLINE (10x 0.23) 1.00 MAX
(10 x 0.55)
0.35
0.200
SEE DETAIL "X" 0.10 C BASE PLANE C 0.20 SIDE VIEW SEATING PLANE 0.08 C
(8x 0.50) C 1.60 0.05 TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. 2. 3. 4. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. Unless otherwise specified, tolerance : Decimal 0.05 Lead width applies to the metallized terminal and is measured between 0.18mm and 0.30mm from the terminal tip. 5. 6. Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature. 0.20 REF 5
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2.00
FN7713.1 December 8, 2010

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